The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device with an extended data output mode and its method of operation.
In a semiconductor memory such as a DRAM, cell data is transmitted from the addressed cell of a cell array to a column selector via bit lines, and the column selector transmits the cell data to a sense amplifier. The sense amplifier amplifies the data and transmits the amplified data to inner input-output buses, and a bus controller transmits the data on the inner input-output buses to data output lines. The data on the data output lines is transmitted to an output terminal via a data output buffer.
An extended data output mode (hereinafter referred to as EDO mode) for a semiconductor memory, with the data output path described above, is a mode for outputting data even after a column address strobe time (tCAS) while maintaining the data output buffer to always be in the enable state. Thus, because cell data have to be transmitted to the output terminal at a predetermined time from address setup, a minimum margin and a maximum margin for data transmission should be ensured on the basis of the column address strobe time (tCAS).
But, if the column address strobe time (tCAS) in the EDO mode is reduced to accelerate the cycle time, the allowable margin for data transmission cannot be ensured in a slow address setup. Also, if the margin width is enlarged to ensure the acceptable margin for data transmission while accelerating the cycle time, degradation of column address cycle (tCAC) speed occurs in a rapid address setup.